1. Field of the Invention
The present invention relates to memory devices based on chalcogenide materials, and methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
However, attempts to reduce the size of the phase change material element and/or the electrodes can result in electrical and mechanical reliability issues of the cell because of failures associated with the small contact surface therebetween. For example, because GST has two stable crystalline states that have different densities, modulation between the two crystalline states and the amorphous state can cause stresses at the interface and within the GST material.
The magnitude of the reset current needed to induce a phase change can be affected by doping the phase change material. Chalcogenides and other phase change materials can be doped with impurities to modify conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon oxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, e.g., U.S. Pat. No. 6,800,504 (metal doping), and U.S. Patent Application Publication No. U.S. 2005/0029502 (nitrogen doping).
U.S. Pat. No. 6,087,674, and its parent U.S. Pat. No. 5,825,046 by Ovshinsky et al., describe forming composite memory material in which phase change material is mixed with relatively high concentrations of dielectric material in order to manage the resistance of the composite memory material. The nature of the composite memory material described in these patents is not clear, because it describes composites as layered structures as well as mixed structures. The dielectric materials described in these patents cover a very broad range.
A number of researchers have investigated the use of silicon oxide doping of chalcogenide material for the purposes of reducing the reset current needed for operation of the memory devices. See, Ryu, et al., “SiO2 Incorporation Effects in Ge2Sb2Te5 Films Prepared by Magnetron Sputtering for Phase Change Random Access Memory Devices”, Electrochemical and Solid-State Letters, 9 (8) G259-G261, (2006); Lee et al., “Separate domain formation in Ge2Sb2Te5—SiOx mixed layer”, Applied Physics Letters 89, 163503 (2006); Czubatyj et al., “Current Reduction in Ovonic Memory Devices”, E*PCOS06 (2006); and Noh et al., “Modification of Ge2Sb2Te5 by the Addition of SiOx for Improved Operation of Phase Change Random Access Memory”, Mater. Res. Soc. Symp. Proc. Vol. 888 (2006). These references suggest that relatively low concentrations of silicon oxide doping in Ge2Sb2Te5 result in substantial increases in resistance and corresponding reductions in reset current. The Czubatyj et al. article suggests that the improvement in resistance in a silicon oxide doped GST alloy saturates at about 10 vol % (6.7 at %), and reports that doping concentrations up to 30 vol % silicon oxide had been tested, without providing details. The Lee et al. publication describes a phenomenon at relatively high doping concentrations around 8.4 at %, by which the silicon oxide appears to separate from the GST after high-temperature annealing to form domains of GST surrounded by boundaries that are primarily silicon oxide.
Research has progressed to provide memory devices that operate with low reset current by adjusting a doping concentration in phase change material, and by providing structures with very small dimensions. One problem with very small dimension phase change devices involves endurance. Specifically, memory cells made using phase change materials can fail as the composition of the phase change material slowly changes with time because of the instability of the amorphous versus crystalline state. For example, a memory cell in which the active region has been reset to a generally amorphous state may over time develop a distribution of crystalline regions in the active region. If these crystalline regions connect to form a low resistance path through the active region, when the memory cell is read a lower resistance state will be detected and result in a data error. See, Gleixner, “Phase Change Memory Reliability”, tutorial. 22nd NVSMW, 2007.
It is therefore desirable to provide memory cells having a small reset current and addressing the issues of data retention discussed above, as well as addressing the reliability issues of small contact surfaces between electrodes and phase change material discussed above.